Job Description: Senior digital IC logic design engineering position available immediately for self-motivated, talented designers. BSEE/MSEE with at least five years of project lead/management experience, as well as supervisorial and mentor capability required. Customer contact experience is also a must. Candidates need a minimum of five years experience designing gate array and standard cell integrated circuits. Full custom IC design experience would be a plus. Qualified candidate should be fluent with Verilog and Synopsys and should have used it for ASIC designs of 30,000 gates or more.

Designs typically push the technology edge at SEI. Designs range in complexity from 10K to 500K gates. Recent projects include a S400 P1394 link controller, an Ultra-SCSI LVD disk controller, 5ns embedded dual port SRAM, GUI accelerator, laser printer engine, ethernet controller and a sound chip, to name a few. An engineer can expect to be typically involved in 2 to 5 different projects per year. Design starting points range from marketing requirement documents to pre-existing designs which require modification. Responsiblities will include direct customer interaction.

Five years of experience using industry standard IC design packages such as Verilog, Viewlogic and Synopsys is required. Familiarity with VHDL, Compass, Pearl (or Motive), HSPICE and Dracula is an additional advantage.

Salary: U.S. $55K-$100K, depending upon experience. Salaried, exempt position. Competitive benefit package. Relocation assistance available.

Our standards are high, but if you feel this is the type of environment and challenge you've been looking for, please contact us and we'll take the next step.

Direct inquiries to:

Teresa Seward
Silicon Engineering, Inc.
269 Mt. Hermon Road, Suite 207
Scotts Valley, CA 95066

fax: 408-438-8509
email: tseward@sei.com

Silicon Engineering is an Equal Opportunity Employer.