Job Description: Digital IC design engineering positions available immediately for self motivated, talented designers. Qualified candidates will have previous experience designing gate array and standard cell integrated circuits. Full custom IC design experience would be a plus. Designers should be fluent with Verilog and Synopsys and should have used it for ASIC designs of 30,000 gates or more.

Designs range in complexity from 10K to 1M gates. Recent projects include a 64 bit RISC CPU, 200Mhz+ RAMDAC, 5ns embedded dual port SRAM, 3V disk controller, GUI accelerator, laser printer engine, ethernet controller, and a sound chip, to name a few. An engineer can expect to be typically involved in 2 to 5 different projects per year. Design starting points range from marketing requirement documents to pre-existing designs which require modification. Responsibilities include direct customer interaction.

Familiarity with industry standard IC design packages such as Verilog, Viewlogic and Synopsys is required. Familiarity with VHDL, Compass, Pearl (or Motive), HSPICE, Dracula is an additional advantage.

Qualifications: Minimum : BS in EE or CS plus 3 years full time industry experience. Desired : MSEE or equivalent and over 5 years full time industry experience There are no positions available for individuals with less experience.

Salary: US$55-100k, depending on experience. Salaried, exempt position. Competitive benefit package. Relocation available.

Our standards are high, but if you feel this is the type of environment and challenge you've been looking for, please contact us and we'll take the next step.

Direct inquiries to:

Teresa Seward
Silicon Engineering, Inc.
269 Mt. Hermon Road, Suite 207
Scotts Valley, CA 95066

fax: 408-438-8509
email: tseward@sei.com

Silicon Engineering is an Equal Opportunity Employer.