SEI has over ten years of experience in digital ASIC design and has a solid track record of success with many of the leading names in the business, including Apple, Adaptec, Lucent, Microsoft, Cirrus Logic, S3, Adobe, and many more.

We take a highly structured, hierarchical approach to ASIC design and complexity management, and have successfully designed ASICs of million gate complexity and more through consistent project management and meticulous attention to detail. We have developed sophisticated design and verification environments to allow us to rapidly design highly complex ICs and verify them across multiple levels of abstraction.

The design process typically starts with one or more customer meetings to determine and specify the exact customer requirements for the chip. We prefer to become involved early in the customer's design process as we can often assist with determining the most efficient system partitioning and help the customer decide on the final feature set. Once the requirements for the chip are nailed down, the implementation can begin.

We work primarily with Verilog as our high-level design language, although VHDL is also supported. The design is developed in a highly structured, hierarchical manner at RTL (Register Transfer Level), with well-defined interfaces between the major blocks. Timing and testability issues are considered up front to avoid problems later in the design flow.

We take a system approach to chip design, and our verification environment will model not just the chip, but also the memory subsystem, the system bus, and any other peripherals the chip will interact with. We believe that this approach of viewing the chip as just part of a larger system with which it must interact seamlessly is key to our long history of first-time success in designing silicon that is immediately functional when first powered up in a system.

The design is verified using automated self-checking test suites wherever possible to ensure consistent and rigorous checking and to allow full regression suites to be run and checked frequently without manual intervention.

We have the full suite of Synopsys logic synthesis and test compiler tools in house, and again use structured methodologies and automated scripting to efficiently synthesize the design to meet timing constraints with the minimum area. We also use Synopsys for static timing and scan insertion.

Regression tests are re-run at gate-level with estimated timing delays using the same verification environment as was used at RTL level, ensuring that the synthesis produced accurate results.

The verified design is released to the fab for layout - this step is known as First Signoff. The fab routes the chip and returns the post-layout netlist with final timing information. We then re-run the same regression tests again to confirm that no timing problems were introduced during routing, and that the final design will function in the system. The final verified design is signed off to the fab for manufacturing at Second Signoff.