For high-volume products, where unit cost is crucial, SEI provides COT (Customer-Owned Tooling) design services, integrating custom SRAM, ROM and analog blocks designed at SEI with random logic arrays developed using ASIC methodologies.

SEI's foundry expertise and understanding of the underlying semiconductor process technology means that we can help the customer with foundry and technology selection. We have direct experience with a large number of foundries and can advise customers on the relative merits of each for their particular application.

Our proprietary library generation technology allows us to quickly generate design libraries for any given foundry and process technology, including Verilog models, Synopsys synthesis models, and layout. Alternatively, vendor-supplied or third party libraries can be used if available.

Logic blocks are designed using ASIC methodologies, coding in HDL and synthesizing to gates which are then laid out using SEI in-house place and route software or third party tools from suppliers such as Cadence or Avant!

Custom blocks such as RAM, ROM, or analog units, including IO cells with particular drive or sense requirements, are designed using custom circuit design methodologies and are laid out using SEI's in-house layout tools.

The final chip is hooked up and verified using Cadence Dracula for LVS, DRC and ERC, converted to Calma (stream) format, and taped out as GDS-II geometry tapes which interface directly to the fab.